CMOS RF Modeling for GHz Communication IC ’ s

نویسندگان

  • Jia - Jiunn Ou
  • Xiaodong Jin
  • Ingrid Ma
  • Chenming Hu
  • Paul R. Gray
چکیده

With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process [1]. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and computationally intense simulations for accurate results. This method becomes prohibitively complex when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range of bias conditions and operating frequencies is desirable. BSIM3v3 has been widely accepted as a standard CMOS model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high frequencies by utilizing a complicated substrate resistance network and extensive modification to the BSIM3v3 source code [2]. This paper first describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies the accuracy of the model to measured data on both device and circuit levels. The new BSIM3v3 RF model is realized with the addition of three resistors R g , R subd , and R subs to the existing BSIM3v3.1 model (shown in Fig. 1). R g models both the physical gate resistance as well as the non-quasi-static (NQS) effect. R subd and R subs are the lumped substrate resistances between the source/drain junctions and the substrate contacts. The values of R subd and R subs may not be equal as they are functions of the transistor layout (illustrated in Fig. 2). To demonstrate the accuracy of the model, s-parameters of the BSIM3v3 RF model, BSIM3v3 model, and measured data of a 0.35µm NMOS device are plotted in Fig. 3. The improvement can be clearly seen from the S 22 but hardly from S 11. A better picture and more physical insight may be obtained by separating the terminal impedance into the real and imaginary parts with the following six parameters, R in = real(1/ y 11) ; C in = −1/ imag(1/ y 11)/ ω ; R out = 1/ real(y 22) ; C out = imag(y 22)/ ω ; g m = real(y 21) ; C fb = −imag(y 12)/ ω , where ω is the frequency in rad/s (gate is port1, drain port2, and body shorted to the source). As …

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Reliability Engineering in Rf Cmos

Dit proefschrift is goedgekeurd door de promotoren: Summary 125 Samenvatting 127 List of publications 129 Dankwoord 131 Chapter 1 Introduction 1.1 RF CMOS The use of mobile wireless communication systems is rapidly increasing. Electronics involved in these systems are typically referred to as RF electronics. RF stands for radio frequencies, a term covering all frequencies of the electromagnetic...

متن کامل

Silicon photonics-wireless interface ICs for micro-/millimeter-wave fiber-wireless networks.

We present two types of Si photonics-wireless interface (PWI) integrated circuits (ICs) realized in standard Si technology. Our PWI ICs convert optical signals into radio-frequency (RF) signals for downlink remote antenna units in fiber-wireless networks. Characterization and modeling of Si avalanche photodetectors (APDs) fabricated in two different Si technologies are carried out and used for ...

متن کامل

Modeling of Substrate Noise Impact on a Single-Ended Cascode LNA in a Lightly Doped Substrate (RESEARCH NOTE)

Substrate noise generated by digital circuits on mixed-signal ICs can disturb the sensitiveanalog/RF circuits, such as Low Noise Amplifier (LNA), sharing the same substrate. This paperinvestigates the adverse impact of the substrate noise on a high frequency cascode LNA laid out on alightly doped substrate. By studying the major noise coupling mechanisms, a new and efficientmodeling method is p...

متن کامل

On-Chip ESD Protection Design for GHz RF Integrated Circuits by Using Polysilicon Diodes in sub-quarter-micron CMOS Process

ESD protection in RF integrated circuits has several considerations: low parasitic capacitance, constant input capacitance, and insensitive to substrate coupling noise. In this paper, a new ESD protection design with polysilicon diodes for RF IC applications is proposed and characterized. The proposed polysilicon diode is constructed by polysilicon layer in a general CMOS process with a central...

متن کامل

RF Modeling of Through Silicon Vias (TSVs) in 3D IC

1. Introduction As the size of transistor keeps shrinking, advance of CMOS technology becomes more difficult and will eventually reach the physical limitation. To continuously reduce the form factor of the system with multiple chips, one straight forward solution is using stacked dies, called three-dimensional integrated circuits (3D IC). Recently, the technology of Through Silicon Vias (TSVs),...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1998